SHA-3 Hardware Overview

Hardware performances of the SHA-3 candidates were evaluated by using an FPGA on SASEBO-GII and an ASIC library. Hardware macros for the comprehensive evaluation were designed with straightforward architectures. The hardware macros for BLAKE, CubeHash, ECHO, Grostl, Hamsi, Luffa, Shabal, Skein were designed by Ohta-Sakiyama Lab., University of Electro-Comunications. The macros for BMW, Fugue, SIMD were provided from Electrical and Computer Engineering Dept. Virginia Polytechnic Institute and State University Blacksburg. Those for JH, SHAvite-3 were designed by Katholieke Universiteit Leuven (COSIC). The source coeds can be used freely for research purposes. For the Keccak implementation, a VHDL source code from the Keccak Website was used.