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Hardware Security Project

Side-channel Attack Standard Evaluation BOard - SASEBO

Side-channel Attack Standard Evaluation Board (SASEBO)>Links

Links

  • National Institute of Advanced Industrial Science and Technology (AIST)
  • Computer Structures Laboratory, Tohoku University
  • Matumoto Laboratory, Yokohama National University (Japanese)
  • Ohta-Sakiyama Laboratory, University of Elector Comunications (Japanese)
  • JCMVP
  • CRYPTREC
  • Toppan Technical Design Center
  • Tokyo Electron Device LTD
  • Cryptographic Hardware and Embedded Systems (CHES)
  • JST/CREST(Core Research for Evolutional Science & Technology)



Side-channel Attack Standard Evaluation Board (SASEBO)/Page Top
  • HOME
  • SASEBO Project
    • Overview
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    • SASEBO-G
    • SASEBO-GII
    • SASEBO-B
    • SASEBO-R
    • SASEBO-W
    • Cryptographic LSI & IP Cores
    • Physical Analysis Attack
    • Quick Start Guide
  • DPA Contest
  • SHA-3 Hardware
    • Overview
    • FPGA and ASIC Implementation
    • H/W Optimization
  • PUF
  • Publication
  • Links
  • Site Map

Last modified: April 1, 2012

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