Side-channel Attack Standard Evaluation Board (SASEBO)>SHA-3 Hardware>Hardware Optimization

H/W Optimized Implementation

Other ASIC Implementations (STMicro 90-nm Standard Cell Library)

AIST and Aoki Lab., Tohoku University are cooperatively developing SHA-3 hardware with various architectures. This page provides the performance results of the developed SHA-3 hardware. The source codes released below are only for the academic use. Reading the conditions and restrictions is strongly recommended.

Algorithm Code Synthesis
Module		 Block
size
[bit]		 S-box Speed Size
[Gates]		 Efficiency
[Kbps/gate]
Max freq
[MHz]		 Clock
Cycles		 Throughput
[Mbps]
SHA-256 source SHA256 512 505.1
349.7
209.2		 72 3,592
2,486
1,488		 15,574
9,563
8,230		 230.6
260.0
180.8
Grøstl
(Normal)		 source GROESTL_256 512 349.7
260.4
113.1		 11 16,275
12,121
5,265		 120,812
70,953
57,908		 134.7
170.8
90.9
Grøstl
(Compact)		 source GROESTL_256 512 348.4
261.8
101.6		 21 8,945
6,382
2,478		 84,053
46,256
34,783		 101.1
138.0
71.2
Keccak source keccak 1,024 1,030.9
552.5
355.9		 24 43,986
23,573
15,184		 55,900
26,501
25,167		 786.9
889.5
603.3
Luffa

(High-Speed)		 source Luffa 256 Bit
Slice		 625.0
552.5
357.1		 5 32,000
28,287
18,286		 60,856
44,290
31,201		 525.8
638.7
586.1
Table 684.9
549.5
350.9		 35,069
28,132
17,965		 62,838
38,274
29,336		 558.1
735.0
612.4
Luffa

(Normal)		 source Luffa Bit
Slice		 1,000.0
552.5
357.1		 9 28,444
15,715
10,159		 39,394
19,736
18,907		 722.0
796.3
537.3
Table 1,087.0
549.5
355.9		 31,258
15,629
10,123		 39,513
19,604
18,933		 791.1
797.2
534.7
Luffa

(Compact 1)		 source Luffa Bit
Slice		 757.6
546.6
355.9		 25 7,758
5,596
3,641		 25,558
17,477
14,710		 303.5
320.2
247.7
Table 862.5
555.6
355.9		 8,463
5,689
3,644		 26,373
16,467
14,817		 320.9
345.5
245.9
Luffa

(Compact 2)		 source Luffa Bit
Slice		 813.0
552.5
358.4		 129 1,613
1,096
711		 24,285
16,801
15,381		 66.4
65.3
46.2
Table 813.0
555.6
358.4		 1,613
1,103
811		 22,500
16,633
15,383		 71.7
66.3
46.2

Reference