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SASEBO Quick Start Quide

The SASEBO Quick Start Guide provides serial interfaces and a sample program to control SASEBO/SASEBO-G/SASEBO-B/SASEBO-GII boards. Verilog-HDL source codes for Xilinx® FPGAs are also available. A sample AES circuit with a composite field S-Box is integrated on the target FPGA xc2vp7 and xc5vlx30/50 for SASEBO/SASEBO-G and SASEBO-GII, respectively. All the block ciphers except the public-key cipher RSA in the target LSI chip are supported for SASEBO-R.





CPA tool

The Correlation Power Analysis (CPA) tool was designed to analyze power and EM waveforms of an AES circuit for the third DPA contest.

H/W Evaluation Environment for Japanese Ciphers

A Hardware performance evaluation environment using SASEBO-GII has been designed for the Japanese e-government recommended ciphers list. The source codes and software of MUGI, the pseudo random number generator developed by Hitachi, Ltd., are not available here.

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