The SASEBO Quick Start Guide provides serial interfaces and a sample program
to control SASEBO/SASEBO-G/SASEBO-B/SASEBO-GII boards. Verilog-HDL source
codes for Xilinx® FPGAs are also available. A sample AES circuit with a composite field
S-Box is integrated on the target FPGA xc2vp7 and xc5vlx30/50 for SASEBO/SASEBO-G
and SASEBO-GII, respectively. All the block ciphers except the public-key
cipher RSA in the target LSI chip are supported for SASEBO-R.