sasebo_gii_ctrl Project Status
Project File:	sasebo_gii_ctrl.ise	Current State:	Programming File Generated
Module Name:	CHIP_SASEBO_GII_CTRL	Errors:	No Errors
Target Device:	xc3s400a-4ft256	Warnings:	26 Warnings
Product Version:	ISE 10.1.03 - Foundation	Routing Results:	All Signals Completely Routed
Design Goal:	Balanced	Timing Constraints:	All Constraints Met
Design Strategy:	Xilinx Default (unlocked)	Final Timing Score:	0 (Timing Report)

 

sasebo_gii_ctrl Partition Summary				[-]
No partition information was found.

 

Device Utilization Summary					[-]
Logic Utilization	Used	Available	Utilization	Note(s)
Number of Slice Flip Flops	220	7,168	3%
Number of 4 input LUTs	228	7,168	3%
Logic Distribution
Number of occupied Slices	216	3,584	6%
Number of Slices containing only related logic	216	216	100%
Number of Slices containing unrelated logic	0	216	0%
Total Number of 4 input LUTs	282	7,168	3%
Number used as logic	162
Number used as a route-thru	54
Number used for Dual Port RAMs	64
Number used as Shift registers	2
Number of bonded IOBs
Number of bonded	61	195	31%
Number of BUFGMUXs	5	24	20%
Number of DCMs	1	4	25%

 

Performance Summary				[-]
Final Timing Score:	0	Pinout Data:	Pinout Report
Routing Results:	All Signals Completely Routed	Clock Data:	Clock Report
Timing Constraints:	All Constraints Met

 

Detailed Reports						[-]
Report Name	Status	Generated	Errors	Warnings	Infos
Synthesis Report	Current	‰Î 9 21 17:30:02 2010	0	4 Warnings	2 Infos
Translation Report	Current	‰Î 9 21 17:30:08 2010	0	10 Warnings	2 Infos
Map Report	Current	‰Î 9 21 17:30:16 2010	0	7 Warnings	20 Infos
Place and Route Report	Current	‰Î 9 21 17:30:43 2010	0	5 Warnings	0
Static Timing Report	Current	‰Î 9 21 17:30:47 2010	0	0	2 Infos
Bitgen Report	Current	‰Î 9 21 17:31:23 2010	0	1 Warning	0

Date Generated: 09/21/2010 - 17:35:47 <