sasebo_gii_ctrl_sp3a50 Project Status
Project File: sasebo_gii_ctrl_sp3a50.ise Current State: Programming File Generated
Module Name: CHIP_SASEBO_GII_CTRL
  • Errors:
No Errors
Target Device: xc3s50a-4ft256
  • Warnings:
27 Warnings
Product Version: ISE 10.1.03 - Foundation
  • Routing Results:
All Signals Completely Routed
Design Goal: Balanced
  • Timing Constraints:
All Constraints Met
Design Strategy: Xilinx Default (unlocked)
  • Final Timing Score:
(Timing Report)
 
sasebo_gii_ctrl_sp3a50 Partition Summary [-]
No partition information was found.
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 220 1,408 15%  
Number of 4 input LUTs 228 1,408 16%  
Logic Distribution     
Number of occupied Slices 216 704 30%  
    Number of Slices containing only related logic 216 216 100%  
    Number of Slices containing unrelated logic 0 216 0%  
Total Number of 4 input LUTs 282 1,408 20%  
    Number used as logic 162      
    Number used as a route-thru 54      
    Number used for Dual Port RAMs 64      
    Number used as Shift registers 2      
Number of bonded IOBs
Number of bonded 61 144 42%  
Number of BUFGMUXs 5 24 20%  
Number of DCMs 1 2 50%  
 
Performance Summary [-]
Final Timing Score: 0 Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrent‰Î 9 21 14:38:39 201004 Warnings2 Infos
Translation ReportCurrent‰Î 9 21 14:40:53 2010010 Warnings0
Map ReportCurrent‰Î 9 21 14:40:58 201007 Warnings20 Infos
Place and Route ReportCurrent‰Î 9 21 14:41:09 201006 Warnings0
Static Timing ReportCurrent‰Î 9 21 14:41:13 2010002 Infos
Bitgen ReportCurrent‰Î 9 21 15:01:00 201001 Warning0

Date Generated: 09/21/2010 - 15:02:43
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