International Journal

• Evaluation of Physical Unclonable Functions for 28-nm Process Field-Programmable Gate Arrays
  Yohei Hori, Toshihiro Katashita, Hyunho Kang, Akashi Satoh, Shinichi Kawamura, and Kazukuni Kobara
  Journal of Information Processing, vol. 22, no. 2, pp. 344-356, April 2014.

• A Fast Power Current Simulation of Cryptographic VLSI Circuits for Side Channel Attack Evaluation
  Daisuke Fujimoto, Toshihiro Katashita, Akihiko Sasaki, Yohei Hori, Akashi Satoh, and Makoto Nagata
  IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol. E96-A, no. 12, pp. 2533-2541, December, 2013.

• Bitstream Protection in Dynamic Partial Reconfiguration Systems Using Authenticated Encryption
  Yohei Hori, Toshihiro Katashita, Hirofumi Sakane, Kenji Toda, and Akashi Satoh,
  IEICE Transaction on Information and Systems, Vol.E96-D, No.11, pp.2333-2343, November 2013.

• A First Report on Electromagnetic and Power Analysis Attacks against 28-nm FPGA Device
  Yohei Hori, Toshihiro Katashita, Akihiko Sasaki, and Akashi Satoh,
  Information - An International Interdisciplinary Journal, Vol.16, No.8(B), pp.5993-6006, 2013.

• PUF Evaluation with Post-processing and Modified Modeling Attack
  Hyunho Kang, Yohei Hori, Toshihiro Katashita, Akashi Satoh, and Keiichi Iwamura
  International Journal of Security and Its Applications (IJSIA), vol. 7, no. 4, pp. 231-241, July, 2013.

• Evaluation of Information Leakage from Cryptographic Hardware via Common-Mode Current
  Yu-ichi Hayashi, Naofumi Homma, Takaaki Mizuki, Takeshi Sugawara, Yoshiki Kayano, Takafumi Aoki, Shigeki Minegishi, Akashi Satoh, Hideaki Sone, Hiroshi Inoue
  IEICE Transactions on Electronics, vol. E95-C, no. 6, pp. 1089-1097, June, 2012.

• Fair and Consistent Hardware Evaluation of Fourteen Round Two SHA-3 Candidates
  Miroslav Knezevic, Kazuyuki Kobayashi, Jun Ikegami, Shin?fichiro Matsuo, Akashi Satoh
  , Unal Kocabas, Junfeng Fan, Toshihiro Katashita, Takeshi Sugawara, Kazuo Sakiyama, Ingrid Verbauwhede, Kazuo Ohta, Naofumi Homma, and Takafumi Aoki, IEEE Transactions on Very Large Scale Integration Systems, vol. 20, no. 5, pp. 827-840, May, 2012.

• A Configurable On-Chip Glitchy-Clock Generator for Fault Injection Experiments
  Sho Endo, Takeshi Sugawara, Naofumi Homma, Takafumi Aoki, and Akashi Satoh
  IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol. E95-A, no. 1, pp. 263-266, January 2012.

• High-Performance Architecture for Concurrent Error Detection for AES Processors
  Takeshi Sugawara, Naofumi Homma, Takafumi Aoki, and Akashi Satoh
  IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol. E94-A, no. 10, pp. 1971-1980, October 2011.

• Systematic Design of RSA Processors Based on High-Radix Montgomery Multipliers
  Atsushi Miyamoto,Naofumi Homma, Takafumi Aoki, Akashi Satoh, and Adi Shamir
  IEEE Transactions on Very Large Scale Integration Systems, vol. 19, no. 7, pp. 1136-1146, July 2011.

• An On-Chip Glitchy-Clock Generator for Testing Fault Injection Attacks
  Sho Endo, Takeshi Sugawara, Naofumi Homma, Takafumi Aoki, and Akashi Satoh,
  Journal of Cryptographic Engineering, vol. 1, no. 4, pp. 265-270, 2011.

• A Design Methodology for a DPA-Resistant Circuit with RSL Techniques
  Daisuke Suzuki, Minoru Saeki, Koichi Shimizu, Akashi Satoh, and Tsutomu Matsumoto
  IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol. E93-A, no. 12, pp. 2497-2508, December 2010.

• Profiling Attack using Multivariate Regression Analysis
  Takeshi Sugawara, Naofumi Homma, Takafumi Aoki, and Akashi Satoh
  IEICE Electronics Express, vol. 7, no. 15, pp. 1139-1144, August 2010.

• Secure Implementation of Cryptogpraphic Modules -Development of Standard Evaluation Environment for Side Channel Attacks-
  Akashi Satoh, Toshihiro Katashita, and Hirofumi Sakane
  Synthesiology - English edition, vol. 3, no. 1, pp. 86-95, July 2010.

• Comparative Power Analysis of Modular Exponentiation Algorithms
  Naofumi Homma, Atsushi Miyamoto, Takafumi Aoki, Akashi Satoh, and Adi Shamir
  IEEE Transactions on Computers, vol. 59, no. 6, pp. 795-807, June 2010.

• High-Performance Hardware Archuitectures for Galois Counter Mode
  Akashi Satoh, Takeshi Sugawara, and Takafumi Aoki,
  IEEE Transaction on Computer, vol. 58, no. 7, pp. 917-930, July 2009.

• A High-Resolution Phase-Based Waveform Matching and Its Application to Side-Channel Attacks
  Naofumi Homma, Sei Nagashima, Takeshi Sugawara, Takafumi Aoki, and Akashi Satoh,
  IEICE Transactions, vol. 91-A, no. 1, pp. 193-202, January 2008.

• ASIC-Hardware-Focused Comparison for Hash Functions MD5, RIPEMD-160, and SHS
  Akashi Satoh and Tadanobu Inoue,
  VLSI Journal, Elsevier Integration - the VLSI Journal, vol.4 0, no. 1, pp. 3-10, January 2007.

• Unified Hardware Architecture for the Secure Hash Standard
  Akashi Satoh,
  Embedded Cryptographic Hardware: Methodologies & Architectures, NOVA Science Publishers, pp. 1-16, 2004.

• On-demand design service innovations
  Shigenori Shimizu, Hiroshi Ishikawa, Akashi Satoh, Toru Aihara
  IBM Journal of Research and Development, vol. 48, no. 5/6: pp. 751-766, 2004.

• A 10 Gbps Full-AES Crypto Design with a Twisted-BDD S-Box Architecture
  Sumio Morioka and Akashi Satoh,
  IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 12, no. 7, pp. 686-691, July 2004.

• A Scalable Dual-Field Elliptic Curve Cryptographic Processor
  Akashi Satoh and Kohji Takano,
  IEEE Transaction on Computer, vol. 52, no. 1, pp. 449-460, January 2003.

• A PostScript Printer Controller Embedded with Lempel-Ziv Data Compression Function
  Akashi Satoh, Makoto Ueda, and Takeshi Satoh,
  Electronics and Communications in Japan (Part II:Electronics), vol. 82, no. 8, pp. 17-26, Augst 1999.

• Area Reduction and Improvements in Speed and Compression Ratio for a Lempel-Ziv Data Compression Circuit Using a Content Addressable Memory
  Akashi Satoh,
  Electrpmocs and Communications in Japan (Part II:Electronics), vol.82, no. 3, pp. 1-10, March 1999.

• Lempel-Ziv-Type High-Speed Data Compression Circuit Using Content Addressable Memmory
  Akashi Satoh and Hideto Niijima,
  Electronics & Communications in Japan (Part II: Electronics), vol. 78, no. 7, pp. 60-67, July 1995.

• A 14-ns 4-Mb CMOS DRAM with 300-mW Active Power
  Toshio Kirihata, Sang H. Dhong, Koji Kitamura, Toshio Sunaga, Yasunao Katayama, Roy E. Scheuerlein, Akashi Satoh, Yoshinori Sakaue, Kentaroh Tobimatsu, Koji Hosokawa, Takaki Saitoh, Takefumi Yoshikawa, Hideki Hashimoto, Michiya Kazusawa,
  IEEE Journal of Solid-State Circuits, vol. 27, no. 9, pp. 1222-1228, September 1992.

• A Pulsed Sensing Scheme with a Limited Bit-Line Swing
  Roy E. Scheuerline, Yasunao Katayama, Yoshinori Sakaue, Akashi Satoh, Toshio Sunaga, Takefumi Yoshikawa, Koji Kitamura, and S. H. Dhong,
  IEEE Journal of Solid-State Circuits, vol. 27, no. 4, pp. 678-682, April 1992.

International Conference

• Development of Hornet Detection Camera System for Smart Beekeeping
  Mitsuki Terada and Akashi Satoh
  IEEE 11th Global Conference on Consumer Electronics (GCCE2022)
  OS-ICT(1)-5, pp.501-504, October 2022.

• Fertilizer Management System for A Compact Hydroponic Planter
  Kaori Uehara, Hiromichi Ikeda,and Akashi Satoh
  IEEE 8th Global Conference on Consumer Electronics (GCCE2019)
  REM-4, pp.1018-1022, October 2019.

• A Hydroponic Planter System to Enable an Urban Agriculture Service Industry
  Akashi Satoh
  IEEE 7th Global Conference on Consumer Electronics (GCCE2018)
  OS-ICE(1)-1, pp.281-284, October 2018.

• A Compact Hardware Design of a Sensor Module for Hydroponics
  Tomohiro Nishimura, Yuji Okuyama, Ayaka Matsushita, Hiromichi Ikeda, and Akashi Satoh
  IEEE 6th Global Conference on Consumer Electronics (GCCE2017)
  OS-ICE(1)-4, October 2017.

• Security Evaluation of Cryptographic Modules Against Side-Channel Attack Using a Biased Data Set
  Masato Matsubayashi, Hendra Gunter, and Akashi Satoh
  IEEE 6th Global Conference on Consumer Electronics (GCCE2017)
  OS-CBS-3, October 2017.

• Clock Glitch Generator on SAKURA-G for Fault Injection Attack Against a Cryptographic Circuit
  Masato Matsubayashi, Jun Ishii, Masahiro Yasuda, and Akashi Satoh
  IEEE 5th Global Conference on Consumer Electronics (GCCE2016)
  OS-CBS-1, October 2016.

• High-Accuracy and Low-Cost Sensor Module for Hydroponic Culture System
  Tomohiro Nishimura, Yuji Okuyama, and Akashi Satoh
  IEEE 5th Global Conference on Consumer Electronics (GCCE2016)
  OS-IOT-6, October 2016.

• GPGPU Software Implementation of Authenticated Encryption Algorithm Minalpher
  Makiko Kosugi and Akashi Satoh
  IEEE 5th Global Conference on Consumer Electronics (GCCE2016)
  OS-ONS-4, October 2016.

• Comparison of Side-Channel Attacks on Cryptographic Circuits Between Old and New Technology FPGAs
  Yu Nomata, Masato Matsubayashi, Kohei Sawada, and Akashi Satoh
  IEEE 5th Global Conference on Consumer Electronics (GCCE2016)
  OS-ONS-6, October 2016.

• Side-channel AttacK User Reference Architecture Board SAKURA-W for Security Evaluation of IC Card
  Masato Matsubayashi and Akashi Satoh
  IEEE 4th Global Conference on Consumer Electronics (GCCE2015)
  SS-RSE-1, pp.565-569, October 2015.

• FPGA Implementation of Authenticated Encryption Algorithm Minalpher
  Makiko Kosugi, Masahiro Yasuda, and Akashi Satoh
  IEEE 4th Global Conference on Consumer Electronics (GCCE2015)
  SS-RSE-3, pp.572-576, October 2015.

• Side-channel AttacK User Reference Architecture SAKURA-G
  Hendra Guntur, Jun Ishii, and Akashi Satoh
  IEEE 3rd Global Conference on Consumer Electronics (GCCE2014)
  SS-CBS-1, pp.271-274, October 2014.

• FPGA Implementation on New Standard Hash Function Keccak
  Tatsuya Honda, Hendra Guntur, and Akashi Satoh
  IEEE 3rd Global Conference on Consumer Electronics (GCCE2014)
  SS-CBS-2, pp.275-279, October 2014.

• SASEBO-GIII: A Hardware Security Evaluation Board Equipped with a 28-nm FPGA
  Yohei Hori, Toshihiro Katashita, Akihiko Sasaki, and Akashi Satoh
  Proceedings of the 1st IEEE Global Conference on Consumer Electronics, (GCCE 2012), pp. 598-601,
  October 2012.

• Performance Evaluation of the First Commercial PUF-embedded RFID
  Hyunho Kang, Yohei Hori, and Akashi Satoh
  Proceedings of the 1st IEEE Global Conference on Consumer Electronics, (GCCE 2012), pp. 5-8
  October 2012.

• Performance of Physical Unclonable Functions with Shift-Register-Based Post-Processing
  Hyunho Kang, Yohei Hori, Toshihiro Katashita, and Akashi Satoh
  International Conference on Security Technology (SecTech 2012), pp. 14-21,
  November 2012.

• Electromacgnetic Side-channel Attack against 28-nm FPGA Device
  Yohei Hori, Toshihiro Katashita, Akihiko Sasaki, and Akashi Satoh
  Proceedings of the 13th International Workshop on Information Security Applications (WISA 2011),
  August 2012.

• Pseudo-LFSR PUF: A Compact, Efficient and Reliable Physical Unclonable Function
  Yohei Hori, Hyunho Kang, Toshihiro Katashita, and Akashi Satoh
  Proceedings of 2008 International Conference on Reconfigurable Computing and FPGAs (Reconfig 2011),
  6A-2, November 2011.

• PUF Evaluation using SASEBO-GII
  Hyunho Kang, Yohei Hori, Toshihiro Katashita, and Akashi Satoh,
  Cryptographic Hardware and Embedded Systems (CHES 2011),
  September 2011 (Poster).

• Side-Channel Attack Standard Evaluation Board SASEBO-W for Smartcard Testing
  Toshihiro Katashita, Yohei Hori, Hirofumi Sakane, and Akashi Satoh,
  Non-Invasive Attack Testing Workshop (NIAT 2011),
  Sepember 2011.

• A Fast Power Current Analysis Methodology Using Capacitor Charging Model for Side Channel Attack Evaluation
  Daisuke Fujimoto, Makoto Nagata, Toshihiro Katashita, Akihiko Sasaki, Yohei Hori, and Akashi Satoh,
  Proceedings of The 4th annual IEEE International Symposium on Hardware-Oriented Security and Trust (HOST 2011),
  pp. 87-92, June 2011.

• How Can We Conduct Fair and Consistent Hardware Evaluation for SHA-3 Candidate?
  Shin'ichiro Matsuo, Miroslav Knezevic, Patrick Schaumont, Ingrid Verbauwhede, Akashi Satoh, Kazuo Sakiyama, and Kazuo Ota,
  The Second SHA-3 Candidate Conference (SHA-3),
  August 2010.

• Information Leakage from Cryptographic Hardware via Common-Mode Current
  Yu-ichi Hayashi, Takeshi Sugawara, Yoshiki Kayano, Naofumi Homma, Takaaki Mizuki, Akashi Satoh, Takafumi Aoki, Shigeki Minegishi, Hideaki Sone, and Hiroshi Inoue,
  Proceedings of IEEE International Symposium on Electromagnetic Compatibility (EMC 2010),
  pp. 109-114, July 2010.

• Development of an on-chip micro shielded-loop probe to evaluate performance of magnetic film to protect a cryptographic LSI from electromagnetic analysis
  Masahiro Yamaguchi, Hideki Toriduka, Shoichi Kobayashi, Takeshi Sugawara, Naofumi Homma, Akashi Satoh, Takafumi Aoki,
  Proceedings of IEEE International Symposium on Electromagnetic Compatibility (EMC 2010),
  pp. 103-108, July 2010.

• Electromagnetic Information Leakage for Side-Channel Analysis of Cryptographic Modules
  Naofumi Homma, Takafumi Aoki, and Akashi Satoh,
  Proceedings of IEEE International Symposium on Electromagnetic Compatibility (EMC 2010),
  pp. 97-102, July 2010.

• Prototyping Platform for Performance Evaluation of SHA-3 Candidates
  Kazuyuki Kobayashi, Jun Ikegami, Miroslav Knezevic, Eric Xu Guo, Shin?fichiro Matsuo, Sinan Huan, Leyla Nazhandali, Unal Kocabas, Junfeng Fan, Akashi Satoh, Patrick Schaumont, Ingrid Ver- bauwhede, Kazuo Sakiyama, and Kazuo Ohta
  Proceedings of The 3rd Annual IEEE International Symposium on Hardware-Oriented Security and Trust (HOST 2010),
  pp. 60-63, June 2010.

• Hardware Implementations of Hash Function Luffa
  Akashi Satoh, Toshihiro Katashita, Takeshi Sugawara, Takafumi Aoki, and Naofumi Homma,
  Proceedings of The 3rd Annual IEEE International Symposium on Hardware-Oriented Security and Trust (HOST 2010),
  pp. 102-106, June 2010.

• Biasing power traces to improve correlation power analysis attacks
  Yongdae Kim, Takeshi Sugawara, Naofumi Homma, Takafumi Aoki, and Akashi Satoh,
  Proceedings of First International Workshop on Constructive Side-Channel Analysis and Secure Design 2010 (COSADE 2010),
  pp. 77-80, February 2010.

• DPA Characteristic Evaluation of SASEBO for Board Level Simulations
  Toshihiro Katashita, Akashi Satoh, Katsuya Kikuchi, Hiroshi Nakagawa and Masahiro Aoyagi,
  Proceedings of First International Workshop on Constructive Side-Channel Analysis and Secure Design 2010 (COSADE 2010),
  pp. 36-39, February 2010.

• Is the Differential Frequency-based Attack Effective against Random Delay Insertion?
  Ye Lu, Kean Hong Boey, Maire O'Neill, John. V. McCanny, and Akashi Satoh,
  Proceedings of IEEE Workshop on Signal Processing Systems (SiPS 2009),
  pp. 51-56, October 2009.

• Side Channel Attack to Magnetic Near Field of Cryptographic LSI and its Countermeasure by means of Magnetic Thin Film
  Masahiro Yamaguchi, Hideki Toriduka, Shoichi Kobayashi, Takeshi Sugawara, Naofumi Homma, Akashi Satoh, and Takafumi Aoki,
  Proceedings of 19th Soft Magnetic Materials Conference (SMM19),
  no. A3-11, September 2009.

• A Design Methodology for a DPA-Resistant Cryptographic LSI with RSL Techniques
  Minoru Saeki, Daisuke Suzuki, Koichi Simizu, and Akashi Satoh,
  Cryptographic Hardware and Embedded Systems (CHES 2009),
  Lecture Notes in Computer Science, vol.5747, pp.189-204, September 2009.

• Differential Power Analysis of AES ASIC Implementations with Various S-box Circuits
  Takeshi Sugawara, Naofumi Homma, Takafumi Aoki, and Akashi Satoh,
  Proceedings of European Conference on Circuit Theory and Design 2009 (ECCTD '09),
  pp. 395-398, August 2009.

• Development of Side-channel Attack Standard Evaluation Emvironment
  Toshihiro Katashita, Akashi Satoh, Takeshi Sugawara, Naofumi Homma, and Takafumi Aoki,
  Proceedings of European Conference on Circuit Theory and Design 2009 (ECCTD '09),
  pp. 403-408, August 2009.

• Mechanism behind Information Leakage in Electromagnetic Analysis of Cryptographic Modules
  Takeshi Sugawara, Yuichi Hayashi, Naofumi Homma, Takaaki Mizuki, Kohei Omura, Shigeki Minegishi, Takafumi Aoki, and Akashi Satoh,
  Proceedings of the 10th International Workshop on Information Security Applications (WISA 2009),
  Lecture Notes in Computer Science, vol.5932, pp. 66-78, August 2009.

• An Analysis of Information Leakage from a Cryptographic Hardware via Common-Mode Current
  Yuichi Hayashi, Takeshi Sugawara, Yoshiki Kayano, Naofumi Homma, Takaaki Mizuki, Akashi Satoh, Takafumi Aoki, Shigeki Minegish, Hideaki Sone, and Hiroshi Inoue,
  Proceedings of 2009 International Symposium on Electromagnetic Compatibility (EMC '09),
  pp. 17-20, July 2009.

• Spectrum Analysis on Cryptographic Modules to Counteract Side-Channel Attacks
  Takeshi Sugawara, Yuichi Hayashi, Naofumi Homma, Takafumi Aoki, Takaaki Mizuki, Hideaki Sone, and Akashi Satoh,
  Proceedings of 2009 International Symposium on Electromagnetic Compatibility (EMC '09),
  pp. 21-24, July 2009.

• Compact and High-speed Hardware Architectures for Hash Function Tiger
  Akashi Satoh,
  Proceedings of 2008 IEEE International Symposium on Circuits and Systems (ISCAS 2009),
  pp. 1401-1404, May 2009.

• Evaluation of Simple/Comparative Power Analysis against an RSA ASIC Implementation
  Atsushi Miyamoto, Naofumi Homma, Takafumi Aoki, and Akashi Satoh,
  Proceedings of 2008 IEEE International Symposium on Circuits and Systems (ISCAS 2009),
  pp. 2918-2912, May 2009.

• An Experimental Comparison of Power Analysis Attacks against RSA Processors on ASIC and FPGA
  Atsushi Miyamoto, Naofumi Homma, Takafumi Aoki, and Akashi Satoh,
  Proceedings of 14th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2009),
  pp. 58-63, March 2009.

• Enhanced Correlation Power Analysis using Key Screening Technique
  Toshihiro Katashita, Akashi Satoh, Takeshi Sugawara, and Takafumi Aoki,
  Proceedings of 2008 International Conference on Reconfigurable Computing and FPGAs (Reconfig '08),
  pp. 403-408, December 2008.

• Bitstream Encryption and Authentication using AES-GCM in Dynamically Reconfigurable Systems
  Yohei Hori, Akashi Satoh, Hirofumi Sakane, and Kenji Toda,
  The 3rd International Workshop on Security (IWSEC 08),
  Lecture Notes in Computer Science, vol. 5312, pp. 261-278, November 2008.

• Systematic design of high-radix Montgomery multipliers for RSA processors
  Atsushi Miyamoto, Naofumi Homma, Takafumi Aoki, and Akashi Satoh,
  Proceedings of IEEE International Conference on Computer Design (ICCD 2008),
  pp. 403-408, October 2008.

• Compact ASIC Architectures for the 512-bit Hash Function Whirlpool
  Takeshi Sugawara, Naofumi Homma, Takafumi Aoki, and Akashi Satoh,
  Proceedings of the 9th Workshop on Information Security Applications (WISA 2008),
  Lecture Notes in Computer Science, vol. 5379 , pp. 28-40, September 2008.

• Bitstream Encryption and Authentication with AES-GCM in Dynamically Reconfigurable Systems
  Yohei Hori, Akashi Satoh, Hirofumi Sakane, and Kenji Toda,
  Proceedings of International Conference on Field Programmable Logic and Applications (FPL 08),
  pp. 23-28, September 2008.

• Chosen-Message SPA Attacks against FPGA-based RSA Hardware Implementations
  Atsushi Miyamoto, Naofumi Homma, Takafumi Aoki, and Akashi Satoh,
  Proceedings of International Conference on Field Programmable Logic and Applications (FPL 08),
  pp. 35-40, September 2008.

• Collision-based Power Analysis of Modular Exponentiation Using Chosen-message Pairs
  Naofumi Homma, Atsushi Miyamoto, Takafumi Aoki, Akashi Satoh, and Adi Shamir,
  Cryptographic Hardware and Embedded Systems (CHES 2008),
  Lecture Notes in Computer Science, vol. 5154, pp. 15-29, August 2008.

• High-performance Concurrent Error Detection Scheme for AES Hardware
  Akashi Satoh, Takeshi Sugawara, Naofumi Homma, and Takafumi Aoki,
  Cryptographic Hardware and Embedded Systems (CHES 2008),
  Lecture Notes in Computer Science, vol. 5154, pp. 100-112, August 2008.

• Enhanced Power Analysis Attack Using Chosen Message Against RSA Hardware Implementations
  Atsushi Miyamoto, Naofumi Homma, Takafumi Aoki, and Akashi Satoh,
  Proceedings of 2008 IEEE International Symposium on Circuits and Systems (ISCAS 2008),
  pp. 3282-3285 (poster), May 2008.

• ASIC Hardware Implementations for 512-Bit Hash Function Whirlpool
  Akashi Satoh,
  Proceedings of 2008 IEEE International Symposium on Circuits and Systems (ISCAS 2008),
  pp. 2917 - 2920, May 2008.

• High-performance ASIC Implementations of the 128-bit Block Cipher CLEFIA
  Taksehi Sugawara, Naofumi Homma, Takafumi Aoki, and Akashi Satoh,
  Proceedings of 2008 IEEE International Symposium on Circuits and Systems (ISCAS 2008),
  pp. 2925-2928, May 2008.

• High-Speed Pipelined Hardware Architecture for Galois Counter Mode
  Akashi Satoh,
  Information Security Conference 2007 (ISC 2007),
  Lecture Notes in Computer Science, vol. 4779, pp. 118-129, October 2007.

• ASIC performance comparison for the ISO standard block ciphers
  Takeshi Sugawara, Naofumi Homma, Takafumi Aoki, and Akashi Satoh,
  The 2nd Joint Workshop on Information Security (JWIS2007),
  pp. 485-498, August 2007.

• High-Speed Parallel Hardware Architecture for Galois Counter Mode
  Akashi Satoh,
  Proceedings of 2007 IEEE International Symposium on Circuits and Systems (ISCAS 2007),
  pp.1863-1866, May 2007.

• A High-performance ASIC Implementation of the 64-bit Block Cipher CAST-128
  Takeshi Sugawara, Naofumi Homma, Takafumi Aoki, and Akashi Satoh,
  Proceedings of 2007 IEEE International Symposium on Circuits and Systems (ISCAS 2007),
  pp. 1859-1862, May 2007.

• SPA against RSA processor with High-Radix Montgomery Multiplier on an FPGA
  Atsushi Miyamoto, Naofumi Homma, Takafumi Aoki, and Akashi Satoh,
  Proceedings of 2007 IEEE International Symposium on Circuits and Systems (ISCAS 2007),
  pp. 1847-1850, May 2007.

• DPA using Phase-Based Waveform Matching against Random-Delay Countermeasure
  Sei Nagashima, Naofumi Homma, Yuichi Imai, Takafumi Aoki, and Akashi Satoh,
  Proceedings of 2007 IEEE International Symposium on Circuits and Systems (ISCAS 2007),
  pp. 1807-1810, May 2007.

• High-Resolution Side-Channel Attack Using Phase-Based Waveform Matching
  Naofumi Homma, Sei Nagashima, Yuichi Imai, Takafumi Aoki, and Akashi Satoh,
  Cryptographic Hardware and Embedded Systems (CHES 2006),
  Lecture Notes in Computer Science, vol. 4249, pp. 187-200, October 2006.

• Evolution of Cryptographic hardware in the Perpetual Security Struggles
  Akashi Satoh,
  2006 Symposium on VLSI Circuit,
  Short Course Lecture, June 2006.

• High-Speed Hardware Architectures for Authenticated Encryption Mode GCM
  Akashi Satoh,
  Proceedings of 2006 IEEE International Symposium on Circuits and Systems (ISCAS 2006),
  May 2006.

• Hardware Architecture and Cost Estimates for Breaking SHA-1
  Akashi Satoh,
  Information Security, 8th International Conference (ISC 2005),
  Lecture Notes in Computer Science, vol. 3650, pp. 259-273, September 2005

• ASIC-Hardware-Focused Comparison for Hash Functions MD5, RIPEMD-160, and SHS
  Akashi Satoh and Tadanobu Inoue,
  Proceedings of International Symposium on Information Technology: Coding and Computing (ITCC 2005),
  vol. 1, pp. 532-537, April 2005.

• Hardware-Focused Performance Comparison for the Standard Block Ciphers AES, Camellia, and Triple-DES
  Akashi Satoh and Sumio Morioka,
  Information Security, 6th International Conference (ISC 2003),
  Lecture Notes in Computer Science, vol. 2851, pp. 252-266, October 2003.

• Unified Hardware Architecture for 128-bit Block Ciphers AES and Camellia
  Akashi Satoh and Sumio Morioka,
  Cryptographic Hardware and Embedded Systems (CHES 2003),
  Lecture Notes in Computer Science, vol. 2779, pp. 304-318, October 2003.

• Compact Hardware Architecture for 128-bit Block Cipher Camellia
  Akashi Satoh and Sumio Morioka,
  Third NESSIE Workshop, November 2002.

• Small and High-Speed Hardware Architectures for the 3GPP Standard Cipher KASUMI
  Akashi Satoh and Sumio Morioka,
  International Security Conference (ISC 2002),
  Lecture Notes in Computer Science, vol. 2433, pp. 48-62, October 2002.

• An Optimized S-Box Circuit Architecture for Low Power AES Design
  Sumio Morioka and Akashi Satoh,
  Cryptographic Hardware and Embedded Systems (CHES 2002),
  Lecture Notes in Computer Science, vol. 2523, pp.172-186, August 2002.

• 10 Gbps Full-AES Crypto Hardware with Twisted-BDD S-Box Architecture
  Sumio Morioka and Akashi Satoh,
  Proceedings of 20th International Conference on Computer Design (ICCD 2002),
  pp. 98-103, September 2002.

• Hardware Resource and Performance Optimization for Elliptic Cureve Cryptography
  Kohji Takano, Akashi Satoh, and Nobuyuki Ohba,
  COOL Chips IV, March 2001.

• A Compact Rijndael Hardware with S-Box optimization
  Akashi Satoh, Sumio Morioka, Kohji Takano, and Seiji Munetoh,
  Advances in Cryptology ( ASIACRYPT 2001),
  Lecture Notes in Computer Science, vol. 2248, pp. 239-254, December 2001.

• TATSU - Hardware Accelerator for Public-Key Cryptography using Montgomery Method
  Kohji Takano, Akashi Satoh, and Nobuyuki Ohba,
  COOL Chips III, April 2000.

• A High-Speed MARS Hardware
  Akashi Satoh, Nobuyuki Ooba, Kohji Takano, and Edward D'Avignon,
  Proceedings of The 3rd Advanced Encryption Standard Candidate Conference (AES3),
  pp. 305-316, April 2000.

• Development of a High Bandwidth Merged Logic/DRAM Multimedia Chip
  Wing K. Luk, Yasunao Katayama, Wei Hwang, M. Wordeman, Toshio Kirihata, Akashi Satoh, Seiji Munetoh, H. Wong, B. El-Kareh, P. Xiao, and Rajiv V. Joshi,
  Proceedings of 1997 International Conference on Computer Design (ICCD '97),
  pp. 279-285, October 1997.

• A High-Speed Small RSA Encryption LSI with Low-Power Dissipation
  Akashi Satoh, Yoshinao Kobayashi, Hideto Niijima, Nobuyuki Ooba, Seiji Munetoh, and Sadamichi Sone,
  Information Security, First International Workshop (ISW '97),
  Lecture Notes in Computer Science, vol. 1396, pp. 174-187, September 1997.

• A Pulsed Sensing Scheme with a Limited Bit-Line Swing
  Roy E. Scheuerline, Yasunao Katayama, Yoshinori Sakaue, Akashi Satoh, Toshio Sunaga, Takefumi Yoshikawa, Koji Kitamura, and Sang H. Dhong,
  Proceedings of 1991 Symposium on VLSI Circuit, May 1991.

Patent

• Electronic circuit component authenticity determination method
  Akashi Satoh, Toshihiro Katashita,
  United States Patent 9,121,873, September 1, 2015.

• Multiplier and cipher circuit
  Akashi Satoh, Koji Takano,
  United States Patent 8,244,790, August 14, 2012.

• Combinational circuit, encryption circuit, method for constructing the same and program
  Sumio Morioka, Akashi Satoh, Gang Zhang,
  United States Patent 7,460,666, December 2, 2008.

• Content play back, information processing, and play back restriction
  Akashi Satoh Koichi Kamijyo,
  United States Patent 7,336,887, February 26, 2008.

• Arithmetic circuit to increase the speed for a modular multiplication for a public key system for encryption
  Akashi Satoh, Kohji Takano,
  United States Patent 6,772,942, August 10, 2004.

• Carry skip adder
  Yoshinao Kibayashi, Akashi Satoh, Seiji Munetoh,
  United States Patent 6,735,612, May 11, 2004.

• Apparatus for calculating of Bc (mod n) with repeatedly shifting a holding value
  Yoshinao Kibayashi, Akashi Satoh, Hideto Niijima,
  United States Patent 6,317,769, November 13, 2001.

• Carry skip adder
  Yoshinao Kibayashi, Akashi Satoh, Seiji Munetoh,
  United States Patent 6,199,091, March 6, 2001.

• Apparatus and method for calculating B.sup.c (mod n)
  Yoshinao Kibayashi, Akashi Satoh, Hideto Niijima,
  United States Patent 5,928,315, July 27, 1999.

• DRAM/SRAM with uniform access time using buffers, write back, address decode, read/write and refresh controllers
  Yasunao Katayama, Akashi Sato,
  United States Patent 5,875,452, February 23, 1999.

• Search circuit for data compression
  Akashi Satoh,
  United States Patent 5,877,714, March 2, 1999.

• Flash-erase-type nonvolatile semiconductor storage device
  Hideto Niijima, Takashi Toyooka, Akashi Satoh, Yoshinori Sakaue,
  United States Patent 5,844,910, December 1, 1998.

• Control method and apparatus for direct execution of a program on an external apparatus using a randomly accessible and rewritable memory
  Hideto Niijima, Akashi Satoh,
  United States Patent 5,787,493, July 28, 1998.

• Content-addressable-memory control circuit
  Akashi Satoh,
  United States Patent 5,740,097, April 14, 1998.

• Flash-erase-type nonvolatile semiconductor storage device
  Hideto Niijima, Takashi Toyooka, Akashi Satoh, Yoshinori Sakaue,
  United States Patent 5,546,402, August 13, 1996.

• Flash-erase-type nonvolatile semiconductor storage device
  Hideto Niijima, Takashi Toyooka, Akashi Satoh, Yoshinori Sakaue,
  United States Patent 5,509,018, April 16, 1996.

• Data search and compression device and method for searching and compressing repeating data
  Akashi Satoh, Hideto Niijima,
  United States Patent 5,448,733, September 5, 1995.